This invention relates to electronic integrated circuits (ICs) of the type having multiple layers of metal interconnects formed on top of one another on a substrate of the IC. More particularly, the present invention relates to a new and improved metal-insulator-metal (MIM) capacitor integrally formed with electrical conductors of an interconnect layer of the IC. Forming the capacitor integrally with the electrical conductors of the interconnect layer facilitates the integration of the capacitor fabrication process into the overall IC fabrication process by using conventional photolithographic and etching process steps to form a capacitor construction of relatively straightforward characteristics and to achieve more precise, predictable and linear response characteristics from the capacitor, among other things.
The ongoing advances in the field of fabricating miniaturized electronic integrated circuits (ICs) has involved the fabrication of multiple layers of interconnects. Interconnects refer to the layer of separate electrical conductors which are formed on top of the substrate and which connect various functional components of the IC. Electrical connections between the interconnect layers and the functional components on the substrate are achieved by xe2x80x9cvia interconnects,xe2x80x9d which are post-like or plug-like vertical connections between the conductors of the interconnect layers and the devices on the surface of the substrate. Presently manufactured ICs often use five or more interconnect layers to connect together components of the IC.
Only a relatively short time ago, it was impossible or very difficult to construct an IC with more than one or two layers of interconnects. The topography variations created by previous layers resulted in a significant depth of focus problem with the lithographic process such that any further additions of layers were nearly impossible to achieve. However, recent advances in semiconductor fabrication planarization techniques, such as chemical mechanical polishing (CMP), have been successful in smoothing relatively significant variations in the height or topography of the previously deposited layers. As a result of the smoothing, or planarization, conventional lithographic processes are repetitively employed without significant limitation to form considerably more layers of interconnects than had previously been possible.
Low resistance metal routes with minimal coupling capacitance are a critical consideration in the design of an IC. Thus, great attention has been focused upon optimizing the distance (space) between interconnect layers. Normally the space between the interconnect layers is occupied by an insulating material, known as an intermetal dielectric (IMD), to insulate the electrical signals conducted by the various conductors of the interconnect layers from each other and from the functional components in the underlying substrate.
One effective use for the space between the interconnect layers is to incorporate capacitors between the interconnect layers in the IMD insulating material separating the interconnect layers. These capacitors form part of the functional components of the IC. Previously, capacitors were constructed alongside other structures, such as transistors, so the capacitors were formed of generally the same material used to construct the functional components on the substrate, such as polysilicon. Capacitors formed of these materials are generally known as poly plate capacitors. The aforementioned inventions described in the referenced U.S. patent applications focus on different techniques for combining capacitors with the conductors of the interconnect layers to achieve desirable functional effects within the IC.
Because the conductors of the interconnect layers are metal in construction, the capacitors formed between the interconnect layers are preferably of a metalin-sulator-metal (MIM) construction to take advantage of processing steps and performance enhancements. A MIM capacitor has metal plates, usually formed on the metal conductors of the interconnect layers. Because metal fabrication is required for the conductors of the interconnect layers, the simultaneous or near-simultaneous formation of the metal capacitor plates is readily accomplished without significant additional process steps and manufacturing costs. The fifth above identified invention describes a technique for the simultaneous formation of the capacitor embedded within an interconnect layer. Thus, at least part of the capacitor is readily fabricated without significant additional process steps and manufacturing costs.
Forming other parts of the capacitor between the interconnects does, however, require additional process steps. The process steps may be particularly difficult to execute when the components of the capacitor are three-dimensional in nature, such as U-shaped capacitor plates, or when the shape of the capacitor plates require unusual configurations for connection to the via interconnects.
A capacitor fabrication technique used to make polycrystalline silicon plate capacitors, poly plate capacitors, is very efficient and well known. Poly plate capacitors have horizontal plates formed in the substrate of the IC using conventional photolithographic and etching techniques. However, the advantages of the familiar and efficient poly plate capacitor fabrication process are difficult or impossible to apply in constructing a capacitor between interconnect layers because of the relative incompatibility of the semiconductor fabrication processes used prior to metal deposition compared to the fabrication processes used afterward to construct the interconnect layers and the IMD insulating material. Since doped polysilicon, a semiconductor, is used as an electrode, the charge within the electrode is spread over a space charge region in the electrode. The speed at which such a capacitor operates is limited because the charge in the electrode is distributed across a space charge region as a capacitor in series with the poly capacitor.
It is with respect to these and other background considerations that the present invention has evolved.
The present invention relates to a new and improved MIM capacitor, and a method of fabricating it, which facilitates the integration of its manufacturing process with the construction of the interconnect layers and the IMD insulating material. The overall process employed is similar to familiar photolithographic and etching steps used to fabricate poly plate capacitors, except that the materials employed are compatible with and integrated with the formation of the conductors of the interconnect layers and the IMD insulating material between the interconnect layers. The capacitor construction itself facilitates using conventional photolithographic and etching steps, and the construction process and materials used make for a straightforward construction of the capacitor plates and their connection to the interconnect layers. The capacitor preferably employs a horizontal plate configuration, with no complex shapes such as trenches, U-shaped plates, cylinders or the like. The capacitor materials and its construction achieve more precise and linear response characteristics. Moreover, one of the plates of the capacitor is integrated with a layer of metal in an interconnect, thereby facilitating the simultaneous fabrication of the interconnect layer and a part of the capacitor. Because of the reliability achieved from the straightforward construction, more control over the capacitive characteristics is achieved. The risks of an improperly formed capacitor and of diminished effectiveness of the IC itself are greatly diminished.
The present invention makes use of a discovery that involves controlling the temperature during the fabrication process to prevent the growth of material grains in the interconnect layer which becomes one of the capacitor plates. By preventing the growth of the material grains in the capacitor plates, deformation of the capacitor plates is avoided and a smooth even configuration of the plates is achieved to preserve the value and precision of the capacitance. In contrast, uneven plates from material grain growth adversely influence the capacitance value as a result of the non-uniform thickness of the dielectric material between the capacitor plates, or may promote shorting of the capacitor plates and destruction of the capacitor.
These and other improvements are achieved in an interconnect-integrated capacitor which is embedded in an IC having an interconnect layer where one of the plates of the capacitor comprises a portion of the interconnect layer. Additional preferred aspects of the present invention relate to the interconnect layer having multiple conductive layers and one of the capacitor plates comprising one of the conductive layers. One of the conductive layers of the interconnect layer is subject to grain growth above a certain temperature, so it is preferred that parts of the capacitor be formed at temperatures below that at which grains in the conductive layer may grow. Preferably, the IC has a second interconnect layer, the interconnect layers are separated by an IMD layer, a top plate of the capacitor is formed between the interconnect layers, and a bottom plate comprises a portion of one of the interconnect layers. Via interconnects preferably electrically connect the second interconnect layer to the top plate and the bottom plate. The via interconnects are of different depths, so it is further preferred that a second dielectric layer, preferably made of the same material as the dielectric layer between the capacitor plates, is on top of the top plate, and both dielectric layers provide etch stops for forming the vias for the via interconnects.
The previously mentioned and other improvements are achieved in a method of fabricating a MIM capacitor in an IC having multiple interconnect layers, which generally involves the steps of forming a capacitor comprising two capacitor plates and using one of the interconnect layers to define one of the capacitor plates. Additional preferred method aspects of the present invention relate to forming a dielectric layer on top of one of the interconnect layers and forming a top plate on top of the dielectric layer. A bottom plate is preferably formed from a portion of the interconnect layer on top of which the dielectric layer is formed. A second dielectric layer, preferably of the same material as the first dielectric layer, is formed on top of the top plate, and both dielectric layers preferably serve as etch stops. Vias are preferably etched through an IMD layer to the top plate and the bottom plate at different depths, and via interconnects are formed therein. Etch stops, such as dielectric layers directly above each plate, are preferably used at different levels to stop each via being etched. The interconnect layer that defines one of the capacitor plates may comprise multiple layers, one of which may be subject to grain growth above a predetermined temperature, so at least part of the capacitor is preferably formed at a temperature below the predetermined temperature.
A more complete appreciation of the present invention and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments of the invention taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.